Skills You Can Build

Write your first SystemVerilog module. Connect logic gates, build a small datapath, and see what changes on each clock cycle.

Both inputs high → output high.

Write a testbench, inspect a waveform, and track a failing test back to the line of hardware code that caused it.

Follow a signal through three clock cycles.

Place chip blocks, route the connections between them, and check whether signals arrive before the next clock edge.

Four blocks settle into a connected layout.

Take a model operation, translate it into processor instructions, and compare the result in a simulator.

A tiny network becomes instructions; the processor produces an output.